Design-Reuse

Unified C-programmable ASIP architecture for multi-standard Viterbi, Turbo and LDPC decoding

This paper describes an ASIP decoder template suitable for multi-standard Viterbi, Turbo and LDPC decoding. We show architecture fitness for WLAN, WiMAX and 3GPPLTE standards, although various other ...
EDN

LDPC: Another Key Step Toward Shannon

For communication designers, especially those in the networking and wireless field, the Shannon limit can be seen as the Holy Grail. And, since being first defined in ...
EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
Total Telecom

AccelerComm’s New Highly Optimised LDPC Decoder in Software for Intel’s FlexRAN Reference Software Will Increase 5G Throughput by up to 3X

AccelerComm, the company supercharging 5G with Optimisation and Latency Reduction IP, today announced they have developed a highly optimised LDPC software decoder in collaboration with Intel. The ...
Design-Reuse

AccelerComm Reduces 5G Latency by up to 16x with NR LDPC Channel Coding

Southampton, UK – 11 th December 2019: AccelerComm, the company supercharging 5G with Optimisation and Latency Reduction IP, announced today the launch and general ...
New Electronics

AccelerComm develops LDPC Decoder for Intel’s FlexRAN

AccelerComm, the company specialising in optimisation and latency reduction IP, has announced they have developed a highly optimised LDPC software decoder in collaboration with Intel. The solution is ...
New Electronics

University of Southampton spin-out unveils breakthrough 5G latency technology

Southampton University spin-out, AccelerComm, has announced the 5G NR LDPC version of its error correction software, which reduces latency up to 16x to support numerology 4 in 3GPP 38.211 and also ...