Electronic Design

All digital phase-locked loop offers sub-mW power consumption

San Francisco, CA. At the 2017 International Solid-State Circuits Conference in San Francisco, imec, Holst Centre, and ROHM presented an all-digital phase-locked loop (ADPLL) for Internet-of-Things ...
Nature

Phase-Locked Loop Design in CMOS Technology

Phase-locked loops (PLLs) are indispensable timing and frequency synthesis circuits, finding application in communication transceivers, clock distribution, navigation receivers and sensor interfaces.
TechRepublic

A Fast Locking Digital Phase-Locked Loop using Frequency Difference Stage

A novel fast locking Digital Phase-Locked Loop (DPLL) has been proposed with simple control unit to improve locking time. A Frequency Difference Stage (FDS) is added to produce a 3-bit code represents ...
Nature

Dynamical response and noise limit of a parametrically pumped microcantilever sensor in a Phase-Locked Loop

The quality factor of MEMS resonant sensors is a key parameter to determine the performance of many sensing applications. Techniques such as Q-control 1, direct feedback or parametric pumping 2 have ...
Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 1)

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...
EurekAlert!

Figure 2. Die micrograph of the proposed digital phase locked loop (PLL) (IMAGE)

The total power consumption of the proposed PLL is only 8.89 mW from a 1 V supply, which leads to a figure of merit of reference of -247.4 dB. Credit must be given to the creator. Only noncommercial ...