EDN

IMEC Extends High-K Program with Metal Gate Stacks

R&D center IMEC has extended its industrial affiliation program (IIAP) on high-k dielectrics for sub-65nm devices to provide solutions for the implementation of metal gate stacks in planar scaled CMOS ...
EDN

IMEC details high-k metal gate planar CMOS progress

At the IEEE International Electron Devices Meeting being held this week, Leuven, Belgium-based nanotechnology research center IMEC is reporting significant progress in improving the performance of ...
WDAF-TV

SIGen Enhances CMOS Performance by 3DIC Wafer Scale Stacking Using Proprietary NANOCLEAVE(TM) Layer Transfer Process

SiGen is a leading provider of engineered substrate process technology and equipment for the semiconductor, display, and optoelectronics markets. SiGen’s technology is used for production of ...
sciencex

Development of a 3-D stacking process for non-volatile MRAM

Researchers have developed a stacking technology for a magneto-resistive random access memory (MRAM) to separately form a single-crystal tunnel magnetoresistive (TMR) thin film and then bond it to a ...
WPRI 12

SIGen Enhances CMOS Performance by 3DIC Wafer Scale Stacking Using Proprietary NANOCLEAVE(TM) Layer Transfer Process

SIGen Enhances CMOS Performance by 3DIC Wafer Scale Stacking Using Proprietary NANOCLEAVE (TM) Layer Transfer Process News provided by EIN Presswire Mar 02, 2023, 9:00 PM ET SiGen Extends Application ...