EDN

SOC-PLL design requires trade-offs

PLLs (phase-locked loops) are common analogcircuits in SOCs (systems on chips). Almost allSOCs with a clock rate greater than 30 MHzuse a PLL for frequency synthesis. However, a“one-size-fits-all” PLL ...
EDN

Good behavioral model simulation: key to predicting first-order PLL synthesizer performance (Part 2 of 2)

The Agilent RFDE and ADS tools provide today's engineer with an accurate, well-defined methodology for predicting first-order phase noise performance of the PLL in the above example. The ...