EDN

Synthesis-friendly RTL called key to first-pass design

SAN MATEO, Calif. — To achieve first-pass timing closure on complex ASICs, designers must ensure their chip architecture design and RTL design are physical synthesis-friendly. That was the bottom-line ...
EDN

BDTI unveils FPGA C-synthesis certification: Can C beat RTL?

With the appearance of higher speeds and more DSP macrocells in low-cost FPGAs, more and more design teams are seeing the configurable chips not as glue, but as a way to accelerate the inner loops of ...
Semiconductor Engineering

Formal Verification Of Synthesizable C++/SystemC Designs

High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this ...
Electronic Design

Synthesis Attacks The Abstract

HARDWARE DESIGN is a process of refining an idea from a highly abstract form to a concrete, physical implementation. Along the way, a design is continually transformed from a given state of ...
Semiconductor Engineering

Simulating HW with C Speed and RTL Accuracy for HLS Designs (Georgia Tech)

A new technical paper titled “OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs” was published by researchers at Georgia Institute of Technology. “High-Level ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...